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NJU6680
128-common x 128-segment 4-level Gray Scale BITMAP LCD DRIVER
GENERAL DESCRIPTION
The NJU6680 is a 128-common x 128-segment 4-level gray scale bit map LCD driver to display graphics or characters. It contains 32,768-bit display data RAM, microprocessor interface circuits, instruction decoder, and common and segment drivers. An image data from CPU through the serial or 8-bit parallel interface are stored into the 32,768-bit internal display data RAM and are displayed on the LCD panel through the commons and segments drivers. The NJU6680 features 4-level gray scale display function creating 4 types of gray scale (white / light gray / dark gray / black) and black & white display function. The NJU6680 contains a built-in OSC circuit for reducing external components. And it features Partial Display Function containing selectable active display block and optimizing the duty cycle ratio. This function dramatically reduces the operating current, setting the optimum boosted voltage combined with a programmable voltage booster circuit and an electrical variable resistor. As result, it reduces the operating current. The operating voltage from 2.2V to 3.6V and low operating current are suitable for small size battery operation items.
PACKAGE OUTLINE
NJU6680CL
FEATURES
Direct Correspondence of Display Data RAM to LCD Pixel Display Method - 4-level Gray Scale / Black & White Display Data RAM - 32,768 bits ;( 128-Com x 128-Seg) x 2bit LCD drivers - 128-common and 128-segment Direct connection to 8-bit Microprocessor interface for both of 68 and 80 type MPU Serial Interface (SI, SCL, RS, CS) Partial Display Function Easy Vertical Scroll by setting the start line address of over size display data RAM Programmable Bias ratio selection ; 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12 bias Useful Instruction Sets Status read, Display data write, Column address set, Page address set, Initial display line set, Initial COM0 line set, Display ON/OFF, Entire display ON/OFF, Reverse display ON/OFF, N-line inversion set, N-line inversion OFF, ADC select, COM scan direction select, Internal resistor ratio set, Power control set, Partial display duty set, LCD bias set, Boost level set, Contrast level set, Power save mode ON, Power save mode OFF, Internal oscillator ON, Display data length set, Reset, FRC & PWM set, Grey scale mode set Display mode set. Power Supply Circuit for LCD; Programmable Booster Circuits (6 times maximum, Voltage boosting polarity : Positive Voltage (VSS Common), Voltage Regulator, Voltage Follower (x 4)) Precision Electrical Variable Resistance (64 Step) Low Operating Current IOUT1=400A (TYP.) Operating Voltage 2.2 to 3.6 V LCD Driving Voltage 6.0 to 18.0V Package Outline Bumped Chip C-MOS Technology ( Substrate : P )
Ver.2003-04-08
-1-
NJU6680
PAD LOCATION
TEST2 DUMMY29 TEST3 DUMMY30 C63 C62 C61 C31 C30 C29 C28 DUMMY31 DUMMY32 DUMMY33
DUMMY34 DUMMY35 DUMMY36 DUMMY37 DUMMY40 DUMMY41 DUMMY42 DUMMY43 DUMMY44 DUMMY45 DUMMY46 C27 C28 C29
C0 S0
X
Y
S127 C64
C89 C90 C91 DUMMY47 DUMMY48 DUMMY49 DUMMY50 DUMMY51 DUMMY52 DUMMY53 DUMMY54 DUMMY55 DUMMY56 DUMMY57 DUMMY58 DUMMY59 C95 C94 C93 C92 DUMMY62 DUMMY61 DUMMY60 TEST5 DUMMY64 TEST4 DUMMY63 C27 C26 C25
DUMMY28 DUMMY27 DUMMY26 DUMMY25 DUMMY22 DUMMY21 DUMMY20 DUMMY19 OSC1 VDD VSS VR V0 V1 V2 V3 V4 VSS INTRS VDD VEXT VSS REF VDD VDD VDD C4+ C2C2+ C1+ C1C3+ C5+ VOUT VSS VCI VDD VDD VDD VDD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD VDD VDD VDD E VSS VSS VSS RW RS VDD VDD VDD RES CS VSS VSS VSS PS1 VDD VDD VDD PS0 VSS VSS VSS TEST1 VDD VDD VDD DUMMY18 DUMMY17 DUMMY16 DUMMY15 DUMMY14 DUMMY13 DUMMY12 DUMMY11 DUMMY10 DUMMY9 DUMMY8 DUMMY7 DUMMY6 DUMMY5 DUMMY4 DUMMY3 DUMMY2 DUMMY1
Chip Center :X=0m,Y=0m Chip Size :X=13.11m,Y=3.08mm Chip Thickness :675um +/- 30um Bump Size :40m x 83m Pad Pitch :60m (min) Bump Height :15m (typ) Bump Material :Au Voltage boosting polarity : Positive Voltage (VSS Common) Substrate :P
2 -2Ver.2003-04-08
NJU6680
PAD Coordinates
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Terminal DUMMY1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DUMMY10 DUMMY11 DUMMY12 DUMMY13 DUMMY14 DUMMY15 DUMMY16 DUMMY17 DUMMY18 VDD VDD VDD TEST1 VSS VSS VSS PS0 VDD VDD VDD PS1 VSS VSS VSS CS RES VDD VDD VDD RS R/W VSS VSS VSS E VDD VDD VDD VDD DB0 DB1 X(um) -6302 -6242 -6182 -6122 -6062 -6002 -5942 -5882 -5822 -5762 -5702 -5642 -5582 -5522 -5462 -5402 -5342 -5282 -5222 -5162 -5102 -4897 -4712 -4652 -4592 -4397 -4209 -4149 -4089 -3892 -3707 -3647 -3587 -3394 -3165 -2982 -2922 -2862 -2669 -2440 -2257 -2197 -2137 -1940 -1760 -1700 -1640 -1580 -1370 -1150 Chip Size Y(um) -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 13.11x3.08mm(Chip Center PAD No. Terminal 51 DB2 52 DB3 53 DB4 54 DB5 55 DB6 56 DB7 57 VDD 58 VDD 59 VDD 60 VDD 61 VCI 62 VSS 63 VOUT + 64 C5 + 65 C3 66 C1 + 67 C1 + 68 C2 69 C2 + 70 C4 71 VDD 72 VDD 73 VDD 74 REF 75 VSS 76 VEXT 77 VDD 78 INTRS 79 VSS 80 V4 81 V3 82 V2 83 V1 84 V0 85 VR 86 VSS 87 VDD 88 OSC1 89 DUMMY19 90 DUMMY20 91 DUMMY21 92 DUMMY22 93 DUMMY23 94 DUMMY24 95 DUMMY25 96 DUMMY26 97 DUMMY27 98 DUMMY28 99 TEST2 100 DUMMY29 X=0m, Y=0m) X(um) Y(um) -930 -1384 -710 -1384 -490 -1384 -270 -1384 -50 -1384 170 -1384 362 -1384 422 -1384 482 -1384 542 -1384 739 -1384 957 -1384 1067 -1384 1284 -1384 1547 -1384 1810 -1384 2073 -1384 2336 -1384 2599 -1384 2862 -1384 3070 -1384 3130 -1384 3190 -1384 3377 -1384 3557 -1384 3754 -1384 3952 -1384 4132 -1384 4315 -1384 4425 -1384 4535 -1384 4645 -1384 4755 -1384 4974 -1384 5084 -1384 5287 -1384 5377 -1384 5558 -1384 5757 -1384 5817 -1384 5877 -1384 5937 -1384 5997 -1384 6057 -1384 6117 -1384 6177 -1384 6237 -1384 6297 -1384 6400 -1273 6400 -1213
Ver.2003-04-08
-3-
NJU6680
PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Terminal TEST3 DUMMY30 COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 DUMMY31 DUMMY32 DUMMY33 DUMMY34 DUMMY35 DUMMY36 DUMMY37 DUMMY38 DUMMY39 DUMMY40 DUMMY41 DUMMY42
X(um) 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6400 6270 6210 6150 6090 6030 5970 5910 5850 5790
Y(um) -1153 -1033 -973 -913 -853 -793 -733 -673 -613 -553 -493 -433 -373 -313 -253 -193 -133 -73 -13 47 107 167 227 287 347 407 467 527 587 647 707 767 827 887 947 1007 1067 1127 1187 1247 1307 1384 1384 1384 1384 1384 1384 1384 1384 1384
PAD No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Terminal DUMMY43 DUMMY44 DUMMY45 DUMMY46 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17
X(um) 5730 5670 5610 5550 5490 5430 5370 5310 5250 5190 5130 5070 5010 4950 4890 4830 4770 4710 4650 4590 4530 4470 4410 4350 4290 4230 4170 4110 4050 3990 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790
Y(um) 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384
4 -4Ver.2003-04-08
NJU6680
PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Terminal SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67
X(um) 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210
Y(um) 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384
PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Terminal SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117
X(um) -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210
Y(um) 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384
Ver.2003-04-08
-5-
NJU6680
PAD No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350
Terminal SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 DUMMY47 DUMMY48 DUMMY49 DUMMY50 DUMMY51 DUMMY52 DUMMY53 DUMMY54 DUMMY55 DUMMY56 DUMMY57 DUMMY58
X(um) -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -3990 -4050 -4110 -4170 -4230 -4290 -4350 -4410 -4470 -4530 -4590 -4650 -4710 -4770 -4830 -4890 -4950 -5010 -5070 -5130 -5190 -5250 -5310 -5370 -5430 -5490 -5550 -5610 -5670 -5730 -5790 -5850 -5910 -5970 -6030 -6090 -6150 -6210
Y(um) 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384
PAD No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394
Terminal DUMMY59 DUMMY60 DUMMY61 DUMMY62 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 DUMMY63 TEST4 DUMMY64 TEST5
X(um) -6270 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400 -6400
Y(um) 1384 1307 1247 1187 1127 1067 1007 947 887 827 767 707 647 587 527 467 407 347 287 227 167 107 47 -13 -73 -133 -193 -253 -313 -373 -433 -493 -553 -613 -673 -733 -793 -853 -913 -973 -1033 -1153 -1213 -1273
6 -6Ver.2003-04-08
NJU6680
BLOCK DIAGRAM
COM0 - - - COM63 SEG0 - - - - - - - SEG127 VDD VSS V0 to V4 Internal Power Circuits V0 VR VEXT INTRS REF VOUT C1+/C1C2+/C2C3
+
COM127 - - - COM64
Common Drivers Voltage Followers
Segment Drivers
Common Drivers
Shift Register
Shift Register
Common Timing Generator
Voltage Regulator
Display Data Latch Row Address Decoder Line Address Decoder
Display Data RAM 128 x 128 x 2 = 32,768-bits
Voltage Converter
C4+ C5+ VCI
Column Address Decoder
Common Direction Page Address Register
Column Address Counter
Column Address Register Oscillator Multiplexer OSC1
Instruction Decoder Internal Bus Line
Status
Busy Flag
Reset
MPU Interface
RES
PS0
PS1
CS
RS
R/W
E
D7 (SI)
Line Counter Display Timing Generator Bus Holder
D6 (SCL)
D5 to D0
Ver.2003-04-08
-7-
NJU6680
TERMINAL DESCRIPTION
*
Power Supply No. Terminal VDD 19-21, 27-29, 36-38, 45-48, 57-60, 71-73, 77,87 VSS 23-25, 31-33, 41-43, 62,75, 79,86 Internal Power Circuits No. Terminal 61 VCI 63 VOUT V0 84 83 V1 V2 82 V3 81 80 V4
Description Power Supply
Ground, 0V
*
Description Voltage converter input terminal Voltage converter output terminal LCD driving voltage terminals * When the internal power circuits are used, the LCD driving voltages (V0 to V4) are enabled by the "Power control set" instruction and an LCD bias ratio is selected by the "LCD bias set" instruction. * When the internal power circuits are not used, the external voltages (V0 to V4) are required on these terminals. The external voltages should be maintained in the relationship: VSS67 66 68 69 65 70 64 85 74
C1 C1 + C2 C2 + C3 + C4 + C5 VR REF
+
76 78
VEXT INTRS
8 -8Ver.2003-04-08
NJU6680
*
MPU Interface Circuits No. Terminal Description Parallel or serial interface select terminal 26 PS0 PS0="L", PS1="L": 3-line serial 30 PS1 PS0="L", PS1="H": 4-line serial PS0="H", PS1="L": 80 type MPU parallel interface PS0="H", PS1="H": 68 type MPU parallel interface 34 CS Chip select terminal Active "L" 56-49 D7-D0 Data bus terminals Parallel interface: D7 to D0 Serial interface: SI (D7 terminal), SCL (D6 terminal) 39 RS Register select terminal * This signal distinguishes instruction data or display data when the LSI is used in the 4-line serial or parallel interface mode. RS="H": D7 to D0 are Display data RS="L": D7 to D0 are Instruction data 44 E 68 type MPU: Active "H" (RD) 80 type MPU: Active "L" 40 R/W 68 type MPU: (WR) R/W="H": Read operation R/W="L": Write operation 80 type MPU: Active "L" 35 RES Reset terminal Active "L" 88 OSC1 OSC terminal * When the internal oscillator is used, the external resistor, Rf, is required between this terminal and the VDD. Rf=270k: Frame frequency=165Hz (typ.) LCD drivers No. Terminal COM0 182-155, 138-103, -311-338, COM127 355-390 182-310 SEG0 -SEG127 Dummy No. 1-18, 89-98, 100,102 139-154, 339-354, 391,393
*
Description Common (row) drivers COM0-COM127 Segment (column) drivers SEG0-SEG127
*
Terminal DUMMY1 -DUMMY64
Description No connections. Dummy pads
*
Test terminals No. Terminal TEST1 22,99, 101,392, -394 TEST5
No connections.
Description Used for maker test
Ver.2003-04-08
-9-
NJU6680
Functional Description
(1) Description of each blocks (1-1) Busy Flag (BF) The BF is used to indicate whether the LSI is busy or not. During the busy status, the LSI cannot accept any instruction except the "Status read" instruction, which reads out the BF through the D7 terminal. When the cycle time (tcyc) mentioned in "AC characteristics" is satisfied, the BF is not required after each instruction so that it is possible to improve the process performance of an MPU. (1-2) Initial display line register The initial display line register is used to specify the DDRAM line address corresponding to the COM0 by the "Initial display line set" instruction. It is used not only for normal display but also vertical scrolling and page switching displays without changing the display data in the DDRAM. (1-3) Line Counter The line counter is used to provide the DDRAM line address. The line address is initialized whenever the polarity of an internal frame signal (FR) is switched, and then it is counted up in synchronization of a common timing signal. (1-4) Column Address Counter An MPU can access only 7-bit [C6:C0] "column address" by the "Column address LSB set" and "Column address MSB set" instructions. When both 4-bit LSB and 3-bit MSB data is set into the column address register, 8-bit "internal column address" is established in the LSI as illustrated in the following figure, and accordingly, 2-bit display data must be written for each pixel with two successive bytes. The column address automatically increases by 1 (+1) after each 2-byte display data and wraps around to the column address (00)H in the same page after the last column is addressed. The assignment of the column address for the segment drivers can be reversed by the "ADC set" instruction.
Segment outputs Internal Column address Column address (ADC=0) Display data Display image SEG0 (00)H (01)H SEG1 (02)H (03)H SEG2 (04)H (05)H SEG3 (06)H (07)H .... .... .... 0 .... .... SEG124 (F8)H (F9)H SEG125 (FA)H (FB)H SEG126 (FC)H (FD)H SEG127 (FE)H (FF)H
(00)H 1 1
(01)H 0 0
(02)H 0 1
(03)H 1
(7C)H 0 1
(7D)H 1 0
(7E)H 1 1
(7F)H 0 0
Column address (ADC=1) Display data Display image
(7F)H 0 0
(7E)H 1 1
(7D)H 1 0
(7C)H 0 1
.... .... ....
(03)H 1 0
(02)H 0 1
(01)H 0 0
(00)H 1 1
(1-5) Page Address Register The page address register is used to provide the DD RAM page address. (1-6) Display data RAM (DD RAM) The Display data RAM (DD RAM) is the bit map RAM consisting of 32,768-bit to store the display data corresponding to 128x128 pixels on LCD panel. Each LCD pixel corresponds to two bits in the display data RAM in gray scale mode and to one bit in black & white mode, display data respectively. The DD RAM data : "00" = Gray Scale Level 0 ( Set by the "Gray Scale Level Select" instruction) The DD RAM data : "01" = Gray Scale Level 1 ( " ) The DD RAM data : "10" = Gray Scale Level 2 ( " ) The DD RAM data : "11" = Gray Scale Level 3 ( " ) The DD RAM data and the state of the LCD in Black & White Mode: In Normal Display : "1"=Turn-On Display, "0" =Turn-Off Display In Reverse Display : "1"=Turn-Off Display, "0" =Turn-On Display
10 - 10 Ver.2003-04-08
NJU6680
First byte Second byte
Page Address Data Display Pattern Line Address Common Outputs
D3,D2,D1,D0 (0,0,0,0)
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 : : : : D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
00000000000000 0123456789ABCD 00 01 02 03 04 05 06
Page 0
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H : : : : 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH
FFFF CDEF 7E 7F
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 : : : : COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127
Initial=(06)H
D3,D2,D1,D0 (0,0,0,1)
Page 1
: : : :
: : : :
D3,D2,D1,D0 (1,1,1,1)
Page 15
Internal Column Address
---------------------
Column Address
ADC=0 ADC=1
[C6:C0] [C6:C0]
---------------------
7F 0
7E 1
7D 2
7C 3
7B 4
7A 5
79 6
01
126
00
127
This is an example for initial display line (06)H.
Segment Outputs
Fig.1 Display data RAM (DDRAM) Map
Ver.2003-04-08
- 11 -
NJU6680
(1-7) Common Direction Register The common direction register is used to select a common scan direction by setting the S0 in the "COM scan direction select" instruction. S0 0 1 COM scan direction COM0 to COM127 COM127 to COM0
(1-8) Reset Circuit The reset circuit is used to initialize the LSI to the following default status by setting the RES terminal to "0" level. Default status by using of the RES terminal 1. Page address : (0) page 2. Column address : (00)H 3. COM scan direction : S0=0 4. ADC select : S0=0 5. Initial display line : (00)H 6. Initial COM0 line : (00)H 7. Display ON/OFF : OFF 8. Reverse display ON/OFF : OFF 9. Entire display ON/OFF : OFF 10. N-line inversion ON/OFF : OFF 11. Partial display duty ratio : 1/128 duty 12. Power control register : (VC,VR,VF)=(0,0,0) 13. Boost level : 3x boost 14. Contrast level : 32 level 15. LCD bias : 1/12 bias 16. Internal resistor ratio : 1+Rb/Ra=2.3 17. Internal oscillator ON/OFF : OFF 18.Power save mode ON/OFF : OFF 19. Display data length : (0,0,0,0) 20. White mode set : OFF 21. White palette register : (0,0,0,0) 22. Light gray mode set : OFF 23. Light gray palette register : (0,0,0,0) 24. Dark gray mode set : OFF 25. Dark gray palette register : (1,1,1,1) 26. Black mode set : OFF 27. Black palette register : (1,1,1,1) 28. FRC & PWM mode : 4-frame, 9-level 29. Display mode set : Gray scale mode The RES terminal is usually connected to the MPU's reset terminal in order that the LSI is initialized at the same timing of the MPU reset. The reset time must be at least 10us or longer, as mentioned in "DC characteristics". The LSI will return to normal operation after about 1us from the rising edge of the rest signal. In case that an external power supply is used for the LCD driving voltage, the RES terminal is required to be maintained in the "0" level when the external power supply is turned on. The "Reset" instruction in Table 3 cannot be substituted for the reset operation by the RES terminal. It can execute only 1,2,5,14,16,19 to 28 items listed above.
12 - 12 Ver.2003-04-08
NJU6680
(1-9) LCD display circuits (a) Common and segment drivers
The common and segment drivers are used to generate LCD driving waveforms in accordance with the combination of display data, common timing signal (CL) and internal frame signal (FL). (b) Display timing generator
The display timing generator is used to generate the common timing signal (CL) and the internal frame signal (FR). The FR signal adopts the 2-frame AC driving method, in which the FR signal is toggled to alternate the crystal polarization on an LCD panel. It toggles on every frame in the default setting or once every N frames in the N-line inversion mode setting, as illustrated in Fig.2-1 and Fig.2-2. (c) Display Data Latch Circuit
The display data latch circuit is used to temporally store the 128-bit display data transferred from the DDRAM and output these display data onto the segment drivers in synchronization of the CL signal. The output timing for the display data, from display latch circuits to segment drivers, is independent of the access timing from MPU to DDRAM. As a result, the LCD display is not affected by the DDRAM access. The "Display ON/OFF", "Reverse display ON/OFF" and "Entire display ON/OFF" instructions control the display data in the display data latch circuit, however they do not change the display data in the DDRAM.
127 128 1
2
3
4
5
6
7
8
9
10 11 12 13
127 128 1
2
3
4
5
6
7
8
9
10 11 12 13
CL
FR
COM0
COM1
SEGn
Duty cycle ratio=1/128 Fig.2-1 LCD driving Waveforms
Ver.2003-04-08
- 13 -
NJU6680
127 128 1
2
3
4
5
6
7
8
9
10 11 12 13
127 128 1
2
3
4
5
6
7
8
9
10 11 12 13
CL
FR
COM0
COM1
SEGn
n=5, Duty cycle ratio=1/128 Fig. 2-2. LCD diving waveforms in the n-line inversion mode
(d)
Oscillator
The internal oscillator is used to create internal clocks for the display timing signals (CL, FR) and the voltage converter.
14 - 14 Ver.2003-04-08
NJU6680
(e) Internal Power Circuits
The internal power circuits are composed of the voltage converter, voltage regulator with 64-level EVR, and voltage followers. The status of the internal power circuits is arranged by the "Power control set" instruction, as shown in Table 1. For this arrangement, the part of the internal power circuits can be used in combination with an external power supply, as shown in Table 2. The internal power circuits require the optimum values for the passive components, such as V0 to V4 capacitors and external feedback resistors in accordance with an LCD panel; and accordingly should be evaluated by using of actual LCD module samples to decide these values.
Bits VC VR VF
Table 1. Power control set Portions Voltage converter Voltage regulator Voltage followers
Status 1: ON 1: ON 1: ON 0: OFF 0: OFF 0: OFF
Combination Using all internal power circuits Using voltage regulator and voltage followers Using voltage followers Using only external power Supply
Table 2. Power supply combinations Instruction Power supply circuits Voltage Voltage Voltage VC VR VF converter regulator followers 1 0 0 0 1 1 0 0 1 1 1 0 ON OFF OFF OFF ON ON OFF OFF ON ON ON OFF
Output terminals VOUT Open External Open Open V0 Open Open External External V1-V4 Open Open Open External
Note) De coupling capacitors on the V0 to V4 terminals are required when the voltage followers are enabled.
Ver.2003-04-08
- 15 -
NJU6680
Power Supply Circuits example
Using all internal power circuits and internal resistors
VOUT C5+ C4+ C3+ Voltage Converter C2+ C2C1+ C1VR INTRS
Using all internal power circuits and external resistors
VOUT C5+ C4+ C3+ Voltage Converter C2+ C2C1+ C1VR V0 V1 V2 V3 V4 INTRS
V0 V1 V2 V3 V4
Using only voltage regulator and internal resistors
Using only external power supply
VOUT C5+ C4+ C3+ External Power Supply C2+ C2C1+ C1VR V0 V1 V2 V3 V4
INTRS
VOUT C5+ C4+ C3+ C2+ C2C1+ C1VR V0 External Power Supply V1 V2 V3 V4
INTRS
Fig. 3. Power circuits configuration
16 - 16 Ver.2003-04-08
NJU6680
(2) Instructions The NJU6680 distinguishes the data on the data bus D0 to D7 as an instruction by combination of RS and R/W signals. The decoding of the instruction and exection performes with only high speed internal timing without relation to the external clock. In case of the serial interface, the data input as MSB(D7) first serially. Table.3-1, 3-2 shows the instruction codes of the NJU6680 Table 3-1. Instruction Codes Code R/W D7 D6 D5 D4 D3 D2 1 Busy ON RES 0 0 0 0 D7 D6 D5 D4 D3 D2 0 0 0 0 0 C3 C2 0 0 0 0 1 0 C6 0 0 0 1 0 0 R2 0 0 0 1 0 1 VC 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 0 * 0 D7 0 * 0 0 1 * 1 1 1 1 1 1 1 1 1 1 1 1 D7 1 L6 1 C6 1 D6 1 * 1 1 0 * 0 0 0 0 0 0 0 1 1 1 1 1 D6 0 L5 0 C5 0 D5 0 * 0 1 0 C5 1 1 1 1 1 1 1 0 1 1 1 1 D5 0 L4 0 C4 0 D4 0 N4 1 0 0 C4 0 0 0 0 0 0 1 0 0 0 0 0 D4 1 L3 0 C3 1 D3 1 N3 0 0 0 C3 0 0 0 1 1 1 P3 S0 0 0 0 1 D3 0 L2 1 C2 0 D2 1 N2 B2 1 0 C2 0 1 1 0 0 1 P2 * 0 0 1 0 D2 FRC
Instruction (a) Status read (b) Display data write (c) (d) (e) (f)
Column address LSB set Column address MSB set Internal resistor ratio set
Power control set Initial display line set (Dual instructions) Initial COM0 line set (Dual instructions) Partial display duty set (Dual instructions) N-line inversion set (Dual instructions) LCD bias set Boost level set Contrast level set (Dual instructions) ADC select Entire display ON/OFF
Reverse display ON/OFF
RS 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D1 0 D1 C1 C5 R1 VR * L1 * C1 * D1 * N1 B1 B1 0 C1 0 0 1 0 1 1 P1 * 0 1 0 0
D0 0 D0 C0 C4 R0 VF * L0 * C0 * D0 * N0 B0 B0 1 C0 S0 E0 R0 1 1 D0 P0 * 1 0 0 0
Descriptions Lower 4-bit Upper 3-bit Set initial display line mode Specify line address Set initial COM0 line mode Specify line address Set partial display mode Specify duty cycle ratio Set N-line inversion mode Specify the number of N-line
(g)
(h)
(i) (j) (k) (l) (m) (n) (o) (p) (q) (r) (s) (t) (u) (v) (w) (x) (y)
Set contrast level mode Specify contrast level Select segment direction E0=0: OFF, E0=1: ON R0=0: OFF, R0=1: ON Power save mode D0=0: OFF, D0=1: ON Select common direction Set display data length
Power save mode ON Internal oscillator ON Display ON/OFF Page address set
COM scan direction select
Power save mode OFF Reset N-line inversion OFF Display data length set (Dual instructions) FRC & PWM set
D0 Specify the data length D1 PWM1 PWM0 (*:Don't Care)
Ver.2003-04-08
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NJU6680
Table 3-2. Instruction Codes Code RS R/W D7 D6 D5 D4 D3 1 0 0 0 1 0 0 WB3 WB2 WB1 WB0 WA3 1 1 0 0 0 0 0 WD3 WD2 WD1 WD0 WC3 1 0 0 0 1 0 0 LB3 LB2 LB1 LB0 LA3 1 0 0 0 1 0 0 LD3 LD2 LD1 LD0 LC3 1 0 0 0 1 0 0 DB3 DB2 DB1 DB0 DA3 1 1 0 0 0 0 0 DD3 DD2 DD1 DD0 DC3 1 1 0 0 0 0 0 BB3 BB2 BB1 BB0 BA3 1 0 0 0 1 0 0 BD3 BD2 BD1 BD0 BC3 0 0 0 0 1 1 1 1 1 1 0 1 1 *
Instruction White mode set, 1st/2nd frame White mode set, 3rd/4th frame Light gray mode set, 1st/2nd frame Light gray mode set, 3rd/4th frame (z) Dark gray mode set, 1st/2nd frame Dark gray mode set, 3rd/4th frame Black mode set, 1st/2nd frame Black mode set, 3rd/4th frame (aa) Display mode set (bb) Test mode
D2 0 WA2 0 WC2 0 LA2 0 LC2 1 DA2 1 DC2 1 BA2 1 BC2 1 *
D1 0 WA1 0 WC1 1 LA1 1 LC1 0 DA1 0 DC1 1 BA1 1 BC1 1 *
D0 0 WA0 1 WC0 0 LA0 1 LC0 0 DA0 1 DC0 0 BA0 1 BC0 DM0 *
Descriptions Specify mode & frame Sets 4-bit pallet registers Specify mode & frame Sets 4-bit pallet registers Specify mode & frame Sets 4-bit pallet registers Specify mode & frame Sets 4-bit pallet registers Specify mode & frame Sets 4-bit pallet registers Specify mode & frame Sets 4-bit pallet registers Specify mode & frame Sets 4-bit pallet registers Specify mode & frame Sets 4-bit pallet registers
DM0=0: Gray scale mode DM0=1: Black & White mode
Don't use. (*:Don't Care)
18 - 18 Ver.2003-04-08
NJU6680
(2-1) Descriptions of the Instruction Codes (a) Status read The "Status read" instruction is used to read out an LSI internal status. It is available only in the parallel interface mode.
RS 0 R/W 1 D7 BUSY D6 ON D5 RES D4 0 D3 0 D2 0 D1 0 D0 0
BUSY
0: The LSI is idle. 1: The LSI is busy and cannot accept any instruction except the "Status read". 0: Display OFF 1: Display ON 0: The LSI is idle. 1: The LSI is executing the reset operation.
ON
RES
(b)
Display data write The "Display data write" instruction is used to write display data into the DDRAM, which address is designated by the "Column address set" and "Page address set" instructions. The column address automatically increases by 1 (+1) after each 2-byte display data and wraps around to the column address 00H in the same page after the last column is addressed. In case that the LSI is used in the 3-line serial interface mode, the "Display data length set" instruction is required before the "Display data write" instruction.
RS 1 R/W 0 D7 D6 D5 D4 D3 Display data D2 D1 D0
Sequence for the display data writing
Page address set
Column address set
Display data write
Column + 1
Yes Data write continue?
No
Ver.2003-04-08
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NJU6680
(c) Column address set The "Column address set" instruction is used to specify the column address for display data. It is required before the "Display data write" instruction. An MPU can access only 7-bit [C6:C0] "column address" by the "Column address LSB set" and "Column address MSB set" instructions. When both 4-bit LSB and 3-bit MSB data is set into the column address register, 8-bit "internal column address" is established in the LSI. For this reason, 2-bit display data must be written for each pixel with two successive bytes. The column address automatically increases by 1 (+1) after each 2-byte display data and wraps around to the column address 00H in the same page after the last column is addressed, and therefore, the DDRAM can be continuously accessed without another "Column address set" instruction.
RS 0 0 C6 0 0 : : 1 1 R/W 0 0 C5 0 0 : : 1 1 D7 0 0 C4 0 0 : : 1 1 D6 0 0 C3 0 0 : : 1 1 D5 0 0 C2 0 0 : : 1 1 D4 0 1 C1 0 0 : : 1 1 D3 C3 0 C0 0 1 : : 0 1 D2 C2 C6 D1 C1 C5 D0 C0 C4 LSB column address MSB column address
Column address 00H 01H : : 7EH 7FH
Internal Column address 00H 01H 02H 03H : : FCH FDH FEH FFH
(d)
Internal resistor ratio set The "Internal resistor ratio set" instruction is used to determine the internal resistor ratio (1+Rb/Ra) for the voltage regulator. For more information, refer to (3-3) "Setting for internal resistor ratio".
RS 0 R2 0 0 0 0 1 1 1 1 R/W 0 R1 0 0 1 1 0 0 1 1 D7 0 R0 0 1 0 1 0 1 0 1 D6 0 D5 1 1+(Rb/Ra) 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2 D4 0 D3 0 D2 R2 D1 R1 D0 R0
(e)
Power control set The "Power control set" instruction is used to configure the internal power circuits. For more information, refer to (3) "Internal power circuits".
RS 0 VC 0 1 R/W 0 VR 0 1 D7 0 VF 0 1 Voltage converter OFF Voltage converter ON Voltage regulator OFF Voltage regulator ON Voltage followers OFF Voltage followers ON D6 0 D5 1 D4 0 D3 1 D2 VC D1 VR D0 VF
20 - 20 Ver.2003-04-08
NJU6680
(f) Initial display line set The "Initial display line set" instruction is used to specify the line address, which corresponds to the initial COM0 line (COM0).
RS 0 0 L6 0 0 0 : 1 1 1 R/W 0 0 L5 0 0 0 : 1 1 1 D7 0 * L4 0 0 0 : 1 1 1 D6 1 L6 L3 0 0 0 : 1 1 1 D5 0 L5 L2 0 0 0 : 1 1 1 D4 0 L4 L1 0 0 1 : 0 1 1 D3 0 L3 L0 0 1 0 : 1 0 1 D2 0 L2 D1 * L1 D0 * L0 Set initial display line Specify line address
Line address 0 1 2 : 125 126 127
(g)
Initial COM0 line set The "Initial COM0 line set" instruction is specify the common driver, which starts scanning the display data in the DDRAM.
RS 0 0 C6 0 0 0 : 1 1 1 R/W 0 0 C5 0 0 0 : 1 1 1 D7 0 * C4 0 0 0 : 1 1 1 D6 1 C6 C3 0 0 0 : 1 1 1 D5 0 C5 C2 0 0 0 : 1 1 1 D4 0 C4 C1 0 0 1 : 0 1 1 D3 0 C3 C0 0 1 0 : 1 0 1 D2 1 C2 D1 * C1 D0 * C0 Set initial COM0 line Specify initial COM0
Initial COM0 COM0 COM1 COM2 : COM125 COM126 COM127
(h)
Partial display duty set The "Partial display duty set" instruction is used to specify the duty cycle ratio for the partial display. The LSI can be programmed to select not only the duty cycle ratio, but also the LCD bias ratio, boost level and contrast level by the instructions so that it is possible to optimize the LSI's condition in accordance with the partial display status. For more information, refer to (7) "Partial display function".
RS 0 0 D7 0 : 0 0 : 1 1 : 1 R/W 0 0 D6 0 : 0 0 : 0 0 : 1 D7 0 D7 D5 0 : 0 0 : 0 0 : 1 D6 1 D6 D4 0 : 0 1 : 0 0 : 1 D5 0 D5 D3 0 : 1 0 : 0 0 : 1 D4 0 D4 D2 0 : 1 0 : 0 0 : 1 D3 1 D3 D1 0 : 1 0 : 0 0 : 1 D2 0 D2 D0 0 : 1 0 : 0 1 : 1 D1 * D1 Duty Invalid 1/16 : 1/128 Invalid D0 * D0 Set partial display duty Specify duty cycle ratio
Ver.2003-04-08
- 21 -
NJU6680
(i) N-line inversion register set The "N-line inversion register set" instruction is used to control the alternate rates of the crystal polarization on an LCD panel. In the N-line inversion mode, the FR signal toggles once every N frames, which number is selected in between 3 and 33 lines, and therefore, prevents a cross talk. If the N-line inversion is disabled by the "N-line inversion mode OFF" instruction, the FR signal toggles by the frame. The number of the N-line should not be set to 1/2 of the display duty cycle ratio in order to avoid generating a DC bias when the partial display is used.
RS 0 0 N4 0 0 : 1 1 R/W 0 0 N3 0 0 : 1 1 D7 0 * N2 0 0 : 1 1 D6 1 * N1 0 0 : 1 1 D5 0 * N0 0 1 : 0 1 D4 0 N4 D3 1 N3 D2 1 N2 D1 * N1 D0 * N0 Set N-line inversion Specify N-line number
Number of N-line 0 3 lines : 32 lines 33 lines
(j)
LCD bias set The "LCD bias set" instruction is used to select the LCD bias ratio. For more information, refer to (3-8) "Voltage followers".
RS 0 B2 0 0 0 0 1 1 1 1 R/W 0 B1 0 0 1 1 0 0 1 1 D7 0 B0 0 1 0 1 0 1 0 1 D6 1 Bias 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12 D5 0 D4 1 D3 0 D2 B2 D1 B1 D0 B0
(k)
Boost level set The "Boost level set" instruction is used to select the multiple for the voltage converter. For detailed information, refer to (3-1) "Voltage converter".
RS 0 B1 0 0 1 1 R/W 0 B0 0 1 0 1 D7 0 Boost 3x 4x 5x 6x D6 1 D5 1 D4 0 D3 0 D2 1 D1 B1 D0 B0
(l)
Contrast level set The "Contrast level set" instruction is used to fine-tune the LCD driving voltage (VLCD) in accordance with an LCD panel. For detailed information, refer to (3-2) "Voltage regulator".
RS 0 0 R/W 0 0 D7 1 * D6 0 * D5 0 C5 D4 0 C4 D3 0 C3 D2 0 C2 D1 0 C1 D0 1 C0 Set contrast level Specify contrast level
22 - 22 Ver.2003-04-08
NJU6680
(m) ADC select The "ADC select" instruction is used to reverse the column address assignment for the segment drivers, so that it is possible to reduce the restriction for the placement of the LSI in an LCD module. For more information, refer to "- Connection between the LSI and LCD panel".
RS 0 S0 0 1 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 S0
Segment direction SEG0 to SEG127 SEG127 to SEG0
(n)
Entire display ON/OFF The "Entire display ON/OFF" instruction is used to enable or disable the entire display, which turns on all pixels without changing the display data in the DDRAM. The "Entire display ON/OFF" instruction has a priority over the "Reverse display ON/OFF" instruction and the "Display ON/OFF" instruction has the priority over the "Entire display ON/OFF" instruction. As a result, even though the "Entire display ON" can be accepted during the "Display OFF", the visual state of the LCD panel does not change.
RS 0 E0 0 1 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 E0
Mode Entire display OFF (Normal) Entire display ON
(o)
Reverse display ON/OFF The "Reverse display ON/OFF" instruction is used to enable or disable the reverse display, which reverses the illumination of each pixel without changing the display data in the DDRAM.
RS 0 R0 0 1 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 R0
Mode Reverse display OFF (Normal) Reverse display ON
Reverse display OFF (Normal) Display data 1 1 Illumination Reverse display ON Display data Illumination
1
0
0
1
0
0
1
1
1
0
0
1
0
0
Ver.2003-04-08
- 23 -
NJU6680
(p) Power save mode ON The "Power save mode ON" instruction is used to enable the power save mode, where it is possible to reduce the power consumption down to stand-by current level. Both of the LSI's internal status and the display data in the DDRAM before the "Power save mode ON" instruction are maintained during the power save mode, in which it is possible to access to the DDRAM. The internal status of the LSI in the power save mode is listed below.
RS 0 R/W 0 Mode Power save mode D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1
Description Oscillator OFF LCD power supply OFF COM/SEG outputs VSS
(q)
Internal oscillator ON The "Internal oscillator ON" instruction is used to enable the internal oscillator. Since the oscillator always turns off after the reset operation, this instruction must be executed for the initialization.
RS 0 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 1 D0 1
(r)
Display ON/OFF The "Display ON/OFF" instruction is used to control the display ON or OFF without changing the display data in the DDRAM. The "Display ON/OFF" instruction has a priority over the "Entire display ON/OFF" and "Reverse display ON/OFF" instructions. Accordingly, even though the "Entire display ON" and "Reverse display ON" instructions can be accepted during the "Display OFF", the visual state of the LCD panel does not change.
RS 0 D0 0 1 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 D0
Mode Display OFF Display ON
(s)
Page address set The "Page address set" instruction is used to specify the page address for display data. It is required before the "Display data write" instruction.
RS 0 R/W 0 D7 1 D6 0 D5 1 D4 1 D3 P3 D2 P2 D1 P1 D0 P0
(t)
COM scan direction select The "COM scan direction select" is used to select the COM scan direction, so that it is possible to reduce the restriction for the placement of the LSI in an LCD module. For more information, refer to "-Connection between the LSI and LCD panel".
RS 0 S0 0 1 R/W 0 D7 1 D6 1 D5 0 D4 0 D3 S0 D2 * D1 * D0 *
COM scan direction COM0 to COM127 COM127 to COM0
24 - 24 Ver.2003-04-08
NJU6680
(u) Power save mode OFF The "Power save mode OFF" instruction is used to release the LSI from the power save mode.
RS 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1
(v)
Reset The "Reset" instruction is used to reset the LSI to the following status. It doesn't change the display data in the DDRAM. It cannot be substituted for the reset operation by the RES terminal. For more information regarding to the reset operation by the RES terminal, refer to (1-8) "Reset circuits".
RS 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0
Reset status by "Reset" instruction 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. (w) Page address Column address Initial display line Contrast level set Internal resistor ratio Display data length White mode set White palette register Light gray mode set Light gray palette register Dark gray mode set Dark gray palette register Black mode set Black palette register FRC, PWM mode : (0) page : (00)H : (00)H : 32 level : 1+Rb/Ra=2.3 : (0,0,0,0) : OFF : (0,0,0,0) : OFF : (0,0,0,0) : OFF : (1,1,1,1) : OFF : (1,1,1,1) : 4-frame, 9-level
N-line inversion mode OFF The "N-line inversion mode OFF" instruction is used to disable the n-line inversion.
RS 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0
(x)
Display data length set The "Display data length set" instruction is used in the 3-line serial interface mode in order to specify the data length in between 1 and 256 bytes for the display data transferred to the DDRAM. The next transferred data after the display data is distinguished as instruction data.
RS 0 0 R/W 0 0 D7 1 D7 D6 1 D6 D5 1 D5 D4 0 D4 D3 1 D3 D2 0 D2 D1 0 D1 D0 0 D0 Set display data length Specify the data length
Ver.2003-04-08
- 25 -
NJU6680
(y) FRC & PWM set The "FRC & PWM set" instruction is used to specify the configuration of PWM and FRC for the 4 gray scale display.
RS 0 FRC 0 1 PWM1 0 0 1 1 R/W 0 D7 1 Frame rate 4-frame 3-frame PWM0 0 1 0 1 PWM level 9-level 9-level 12-level 15-level D6 0 D5 0 D4 1 D3 0 D2 FRC D1 PWM1 D0 PWM0
(z)
Gray scale mode and register set The "Gray scale mode and register set" instruction is composed of two bytes and is used to specify the contrast level for each of the gray scale modes. The first byte specifies the gray scale mode and the frame number, and then the second byte sets pallet values into the specified 4-bit pallet register. For detailed information regarding the gray scale function, refer to (5) "Gray scale function".
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D7 1 WB3 1 WD3 1 LB3 1 LD3 1 DB3 1 DD3 1 BB3 1 BD3
D6 0 WB2 0 WD2 0 LB2 0 LD2 0 DB2 0 DD2 0 BB2 0 BD2
D5 0 WB1 0 WD1 0 LB1 0 LD1 0 DB1 0 DD1 0 BB1 0 BD1
D4 0 WB0 0 WD0 0 LB0 0 LD0 0 DB0 0 DD0 0 BB0 0 BD0
D3 1 WA3 1 WC3 1 LA3 1 LC3 1 DA3 1 DC3 1 BA3 1 BC3
D2 0 WA2 0 WC2 0 LA2 0 LC2 1 DA2 1 DC2 1 BA2 1 BC2
D1 0 WA1 0 WC1 1 LA1 1 LC1 0 DA1 0 DC1 1 BA1 1 BC1
D0 0 WA0 1 WC0 0 LA0 1 LC0 0 DA0 1 DC0 0 BA0 1 BC0
White mode set, 1st/2nd frame 4-bit pallet registers White mode set, 3rd/4th frame 4-bit pallet registers Light gray mode set, 1st/2nd frame 4-bit pallet registers Light gray mode set, 3rd/4th frame 4-bit pallet registers Dark gray mode set, 1st/2nd frame 4-bit pallet registers Dark gray mode set, 3rd/4th frame 4-bit pallet registers Black mode set, 1st/2nd frame 4-bit pallet registers Black mode set, 3rd/4th frame 4-bit pallet registers
(aa) Display mode set The "Display mode set" instruction is used to select either "Gray scale mode" or "Black & White mode". For more information, refer to (6) "Black & White mode".
RS 0 DM0 0 1 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 DM0
Display mode Gray scale mode Black & White mode
(bb) Test mode This instruction is used only for manufacturer's tests.
RS 0 R/W 0 D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 *
26 - 26 Ver.2003-04-08
NJU6680
(3) Internal power circuits The internal power circuits are composed of the voltage converter, voltage regulator with 64-level EVR, and voltage followers. The status of the internal power circuits is arranged by the "Power control set" instruction, as shown in Table 4. For this arrangement, the part of the internal power circuits can be used in combination with an external power supply, as shown in Table 5. The internal power circuits require the optimum values for the passive components, such as V0 to V4 capacitors and external feedback resistors in accordance with an LCD panel; and accordingly should be evaluated by using of actual LCD module samples to decide these values. Table 4. Power control set
Bits VC VR VF Portions Voltage converter Voltage regulator Voltage followers 1: ON 1: ON 1: ON Status 0: OFF 0: OFF 0: OFF
Table 5. Power supply combinations
Instruction Combination Using all internal power circuits Using voltage regulator and voltage followers Using voltage followers Using only external power Supply VC 1 0 0 0 VR 1 1 0 0 VF 1 1 1 0 Power supply circuits Voltage Voltage Voltage converter regulator followers ON ON ON OFF OFF OFF ON OFF OFF ON ON OFF Output terminals VOUT Open External Open Open V0 Open Open External External V1-V4 Open Open Open External
Note) Decoupling capacitors on the V0 to V4 terminals are required when the voltage followers are enabled.
Ver.2003-04-08
- 27 -
NJU6680
(3-1) Voltage converter The voltage converter is designed to generate a maximum 6x voltage from the voltage difference between the VCI and VSS terminals. It is programmed so that the boost level can be selected out of 3x, 4x, 5x or 6x by the "Boost level set" instruction. Since the voltage converter operates by using of the internal clocks supplied from the oscillator, the oscillator is required to be working during the voltage converter operation. The boosted voltage VOUT must not exceed beyond the 18.0V described in "Absolute maximum ratings". Otherwise, the voltage stress may cause a permanent damage to the LSI. Fig.4 illustrates the capacitor connections for the voltage converter.
3x boost
4x boost
5x boost
6x boost
VSS
Cout
VSS
Cout
VSS
Cout
VSS
Cout
VOUT C5+ C3+ C1C1
VOUT C5+ C3+
C3
VOUT C5+ C3+
C3
VOUT C5+
C5
C3+
C3
C1C1
C1C1
C1C1
C1+ C2+
C2
C1+ C2+
C2
C1+ C2+
C2
C1+ C2+
C2
C2C4+
C2C4+
C2C4
C2C4
C4+
C4+
[Reference values: Cout, C1 to C5=1.0 to 4.7uF]
VOUT=6x (VCI-VSS) VOUT=5x (VCI-VSS) VOUT=4x (VCI-VSS) VOUT=3x (VCI-VSS)
VCI VSS
VCI VSS
VCI VSS
VCI VSS
Fig.4 Capacitors connections for the voltage converter
28 - 28 Ver.2003-04-08
NJU6680
(3-2) Voltage regulator The voltage regulator is composed of the reference voltage generator, 64-level EVR, operational amplifier, and internal (or external) feedback resistors, as illustrated in Fig.5 and used to generate the LCD driving voltage V0. In the voltage regulator, the reference voltage VREF is gained with the EVR to produce regulated voltage VCON, which is used for the input voltage of the internal operational amplifier. Namely, the V0 is determined in accordance with the setting for the EVR and internal (or external) resistor ratio, as calculated by the following equations [1] and [2].
VOUT
V0 = (1+Rb/Ra) x VCON VCON = (1-(63-n)/210) x VREF
V0 Rb
[1] [2]
VCON Ra
VR
V0 Ra, Rb VCON n VREF
: LCD driving voltage : Feed back resistors : Contrast control voltage : Parameter decided instruction : Reference voltage
VSS
Fig.5 Voltage regulator (3-3) Setting for internal resistor ratio Either external or internal feedback resistors can be selected by setting the INTRS terminal to "0" or "1", as shown in Table 6. In case that the internal resistors are used, the resistor ratio (1+Rb/Ra) can be selected by the "Internal resistor ratio" instruction, as listed in Table 7. Table 6. Setting for the INTRS terminal
INTRS 0 1 Ra, Rb External resistors Internal resistors
Table 7. Setting for the intrenal resistor ratio
R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 1+(Rb/Ra) 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2
(3-4)
Contrast control voltage VCON In the equation [2], the VCON depends on the parameter "n", which is determined in between 0 and 63 by the "Contrast level set" instruction. Table 8. Setting for the contrast level
C5 0 : 1 C4 0 : 1 C3 0 : 1 C2 0 : 1 C1 0 : 1 C0 0 : 1 n 0 : 63 VCON MIN. : MAX.
Ver.2003-04-08
- 29 -
NJU6680
(3-5) Reference voltage VREF Either external or internal reference voltage VREF is selected by setting the REF terminal to "0" or "1", as shown in Table 9. When the internal reference voltage VREF is selected, the VREF is designed to be 2.1V Typ. and its temperature coefficient becomes -0.125%/C Typ. Table 9. Setting for the REF terminal
REF 0 1 VREF (V) External voltage on the VEXT terminal Internal voltage (VREF=2.1V Typ.) Temperature coefficient -0.125%/C Typ.
(3-6)
Range for the contrast control The LCD driving voltage V0 is determined in accordance with the setting for the EVR and the internal (or external) resistor ratio. Fig.6 graphs the range for the contrast control using the "Contrast level set" and "Internal resistor set" instructions.
16.0 111 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 0 7 15 23 31 47 55 63 110 101 100 011 010 001 000 Internal Resistor Set
V0 [V]
Contrast level set
Fig.6 Range for the contrast control
30 - 30 Ver.2003-04-08
NJU6680
(3-7) Using external Ra and Rb resistors In case that the external feedback resistors (Ra, Rb) are used by setting the INTRS terminal to "0", these external resistors are required to be placed between the VSS and VR and between the VR and V0 terminals. The LCD driving voltage V0 is determined in accordance with the setting for the EVR and the external resistor ratio (1+Rb/Ra) in the following equations [1] and [2], as well as the setting in using the internal resistors Ra and Rb. V0 = (1+Rb/Ra) x VCON [1] VCON = (1-(63-n)/210) x VREF [2]
V0 Ra, Rb VCON n VREF : LCD driving voltage : Feed back resistors : Contrast control voltage : Parameter decided instruction : Reference voltage
The following calculations describe the setting example to decide the external resistors Ra and Rb values. Requirements: 1.LCD driving voltage V0=14.0V (when the contrast level parameter "n"=32) 2.The maximum current flowing through the external Ra and Rb = 5uA Calculations: Following the equation [2], VCON = (1-(63-32)/210) X 2.1V = 1.79V Following the equation [1], Rb/Ra = V0/VCON - 1 = 14.0V/1.79V - 1 = 6.821 -----[A] Following the requirement 2, Ra+Rb = 14.0V/5uA = 2.8M ohm -----[B] Finally, the values for the Ra and Rb are determined by the results [A] and [B], Ra = 0.358M ohm Rb = 2.442M ohm
Contrast level [n] 0 : 32 : 63 V0 [V] 11.5V : 14.0V : 16.4V
(3-8)
Voltage followers The voltage followers are used to stabilize and output the LCD driving voltages (V0, V1, V2, V3 and V4), which are produced by the internal bleeder resistors. It can be programmed to select the LCD bias in the range of 1/5 and 1/12 by the "LCD bias set" instruction. Generally, the optimum bias ratio is determined by the following equation: LCD bias ratio=1/(1+(duty ratio)). For instance, in case of 1/80 duty cycle ratio, it should be 1/10 in accordance with the calculation: 1/(1+(80)). When the voltage followers are used, the capacitors for the V0 to V4 terminals are required in order to stabilize the LCD driving voltages and should be in between 0.47uF and 2.0uF.
Ver.2003-04-08
- 31 -
NJU6680
Using all internal power circuits and internal resistors
VOUT C5+ C4+ C3+ Voltage Converter C2+ C2C1+ C1VR INTRS
Using all internal power circuits and external resistors
VOUT C5+ C4+ C3+ Voltage Converter C2+ C2C1+ C1VR INTRS
V0 V1 V2 V3 V4
V0 V1 V2 V3 V4
Using only voltage regulator and internal resistors
Using only external power supply
VOUT C5+ C4+ C3+ External Power Supply C2+ C2C1+ C1VR
INTRS
VOUT C5+ C4+ C3+ C2+ C2C1+ C1VR
INTRS
V0 V1 V2 V3 V4 External Power Supply
V0 V1 V2 V3 V4
Fig.7 Power circuits configuration
32 - 32 Ver.2003-04-08
NJU6680
(4) MPU Interface (4-1) Interface type selection The interface type (the parallel or serial interface) is determined by the condition of the PS0 and PS1 terminals connecting to "H" or "L" level as shown in Table 10.In the 3- or 4- line serial interface mode, the "Status read" instruction cannot be used. Table 10
PS0 L L H H PS1 L H L H Type 3-line serial 4-line serial 80-type MPU parallel 68-type MPU parallel CS CS CS CS CS RS * RS RS RS E * * RD E W/R * * WR R/W Data bus terminals SI,SCL SI,SCL D7 to D0 D7 to D0
*:Don't care
(4-2) Parallel interface In the 68- or 80- type PU parellel inter face mode, the transferred data on the D7 to D0 terminals is processed in accordance with the polarities of the RS,E(RD),and R/W(WR) signals as shown in table 11. Table 11 Data Distinction
CS L L L L RS H H L L E H H H H 68 type R/W H L H L 80 type RD WR L H H L L H H L Operation None Write display data Read out status read Write instruction data
(4-3) Serial Interface In the serial interface mode, when the chip select is active(CS="0") the SI and SCL are enabled. While the chip select is not active (CS="1"), the SI & SCL are disabled and the internal 8-bit shift register and the 3-bit counter are being initialized. The 8-bit serial data on the SI terminal is fetched at the at the rising edge of the SCL signals in order of D7, D6...D0 data ,and the fetched data is converted into 8-bit parallel th data on the 8 SCL signals. (a) 4-line serial interface In the 4-line serial interface mode, the transferred data on the SI terminal is distinguished as display data or instruction data in accordance with the polarity of the RS signal at the 8th SCL signal, as illustrated in Fig. 8-1.
CS SI SCL RS
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
Fig. 8-1
4-line serial interface timing
Ver.2003-04-08
- 33 -
NJU6680
(b) 3-line serial interface In the 3-line serial interface mode, the "Display data length set" instruction is used to specify the data length in between 1 and 256 bytes for the display data transferred to the DDRAM. The "Display data length set" instruction is executed by 2 bytes data, after which the display data can be continuously transferred. The next transferred data after the display data is distinguished as instruction data. Fig 8-2 illustrates the timing and setting example for the data transmission in the 3-line serial interface mode. When the chip select becomes non-active (CS="1") during a serial display data stream, the interrupted byte data is invalid, however all previous transferred display data is valid and next transferred data will be distinguished as instruction data.
CS
Page address sets Column address set 3 bytes
Display data length set (Dual instructions) 2 bytes LSB
Display data write 1 - 256 bytes Display data
SI
Page
MSB
0
7
8
15
16
23
0
7
8
15
0
SCL
* The setting example for the data transmission in the 3-line serial interface mode. Page address set (1, 0, 1, 1, P3, P2, P1, P0) Column address LSB set: (0, 0, 0, 1, 0, C6, C5, C4) Column address MSB set (0, 0, 0, 0, C3, C2, C1, C0) Display data length set (dual instructions) Set display data length (1, 1, 1, 0, 1, 0, 0, 0) Specify the data length (D7, D6, D5, D4, D3, D2, D1, D0) Display data write
Fig 8-2
3-line serial interface timing
34 - 34 Ver.2003-04-08
NJU6680
(5) Gray scale function (5-1) FRC (Frame Rate Control) and PWM (Pulse Width Modulation) The 4-gray scale function is controlled by the setting for the FRC and PWM configurations and the palette values into the 4-bit palette registers, and provides required gray scale levels. This setting is executed by the "FRC & PWM set" and "Gray scale mode and register set" instructions, as described in the following. FRC & PWM set The "FRC & PWM set" instruction is used to specify the PWM and FRC configurations.
RS 0 FRC 0 1 PWM1 0 0 1 1 R/W 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 FRC D1 PWM1 D0 PWM0
(5-2)
Frame rate 4-frame 3-frame PWM0 0 1 0 1 PWM level 9-level 9-level 12-level 15-level
(5-3)
Gray scale mode & Register set The "Gray scale mode and register set" instruction is composed of two bytes and used to specify the contrast level for each of the gray scale modes. The first byte specifies the gray scale mode and frame number and then the second byte sets the pallet value into the specified 4-bit pallet register.
R/W 0 0 GM1 0 0 1 1 0 0 1 1 D7 1 D6 D5 0 0 4-bit pallet register D4 0 D3 1 D2 D1 GM2 GM1 4-bit pallet register D0 GM0 Gray scale mode & frame 4-bit pallet register set
RS 0 0 GM2 0 0 0 0 1 1 1 1
GM0 0 1 0 1 0 1 0 1
Gray scale mode & Frame 1st/2nd frame White mode 3rd/4th frame 1st/2nd frame Light gray mode 3rd/4th frame 1st/2nd frame Dark gray mode 3rd/4th frame 1st/2nd frame Black mode 3rd/4th frame
Ver.2003-04-08
- 35 -
NJU6680
(5-4) Setting tables for the FRC and PWM Table 12-1. Gray scale table for the 4-FRC
Gray scale level White Light gray Dark gray Black Display data 00 01 10 11 MSB (D7 to D4) 2nd frame 4th frame 2nd frame 4th frame 2nd frame 4th frame 2nd frame 4th frame LSB (D3 to D0) 1st frame 3rd frame 1st frame 3rd frame 1st frame 3rd frame 1st frame 3rd frame
Table 12-2. Gray scale table for the 3-FRC
Gray scale level White Light gray Dark gray Black Display data 00 01 10 11 MSB (D7 to D4) 2nd frame * 2nd frame * 2nd frame * 2nd frame LSB (D3 to D0) 1st frame 3rd frame 1st frame 3rd frame 1st frame 3rd frame 1st frame 3rd frame
*
Note) *: Don't care. Table 13. Gray scale table for the PWM
4-bit palett register 0,0,0,0 0,0,0,1 0,0,1,0 0,0,1,1 0,1,0,0 0,1,0,1 0,1,1,0 0,1,1,1 1,0,0,0 1,0,0,1 1,0,1,0 1,0,1,1 1,1,0,0 1,1,0,1 1,1,1,0 1,1,1,1 9-PWM 0 1/9 2/9 3/9 4/9 5/9 6/9 7/9 8/9 1 0 0 0 0 0 0 12-PWM 0 1/12 2/12 3/12 4/12 5/12 6/12 7/12 8/12 9/12 10/12 11/12 1 0 0 0 15-PWM 0 1/15 2/15 3/15 4/15 5/15 6/15 7/15 8/15 9/15 10/15 11/15 12/15 13/15 14/15 1
36 - 36 Ver.2003-04-08
NJU6680
(6) Black & White mode As an extended function, the LSI is designed to support the black & white mode, which can be switched from the gray scale mode by the "Display mode set" instruction. The gray scale mode is set in the default status. (6-1) Display mode set instruction The "Display mode set" instruction is used to select either gray scale or black & white mode. It is required that the "Display OFF" instruction and DDRAM initialization are executed before the "Display mode set" instruction.
RS 0 DM0 0 1 R/W 1 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 DM0
Display mode Gray scale mode Black & White mode
(6-2) Display data RAM (DDRAM) Although the DDRAM's capability in the gray scale mode is 32,768-bit (128-line by 256-column) for the LCD panel with up to 128x128 pixels, the capability in the black & white mode is 16,384-bit out of the total memory area, as illustrated in the Fig 9. In the black and white mode, 1-bit display data is used for 1-pixel. (6-3) Column address set In the black & white mode, an MPU can access 7-bit [C6:C0] column address by the "Column address LSB set" and "Column address MSB set" instructions. The column address automatically increases by 1 (+1) after each 1-byte display data.
(6-4)
Display data length set The "Display data length set" instruction is used in the 3-line serial interface mode in order to specify the data length in between 1 and 128 bytes in the black & white mode. The D7 bit in the "Display data length set" instruction must be "0".
RS 0 0 R/W 0 0 D7 1 (D7) (D7) D6 1 D6 D5 1 D5 D4 0 D4 D3 1 D3 D2 0 D2 D1 0 D1 D0 0 D0 Set display data length Specify the data length
: Must be "0" in the black & white mode
Ver.2003-04-08
- 37 -
NJU6680
Page Address
Data
Display Pattern
Line Address
Common Outputs
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 : : : : D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H : : : : 75H 76H 77H 78H 79H Page 15 7AH 7BH 7CH 7DH 7EH 7FH
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 : : : : COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127
D3,D2,D1,D0 (0,0,0,0)
Page 0
Initial=(06)H
D3,D2,D1,D0 (0,0,0,1)
Page 1
: : : :
: : : :
D3,D2,D1,D0 (1,1,1,1)
Column Address
ADC=0 ADC=1
00
01
02
03
04
05
06
[C6:C0] [C6:C0] .............................
7E
7F
This is an example for initial display line (06)H.
01
126
7F 0
7E 1
7D 2
7C 3
7B 4
7A 5
79 6
00
127
Segment Outputs
Fig.9 Display data RAM (DDRAM) Map in the Black & White mode
38 - 38 Ver.2003-04-08
NJU6680
(7) Partial display function The partial display function is used to specify optimum duty cycle ratio, LCD bias ratio, boost level and LCD driving voltage to partially display active area on an LCD panel, so that it is possible to display the time and calendar under extremely low power consumption state. It can be programmed to select the duty cycle ratio, LCD bias ratio, boost level and EVR level by the instructions. Fig.10-1 illustrates normal display image and Fig.10-2, 10-3 and 10-4 illustrate the partial display images. The setting sequence for the partial display is described in Fig.15.
COM0
COM8 COM9
COM15
COM112
COM119 COM120
COM127
Fig.10-1 Normal display image (duty cycle ratio=1/128, COM0=0)
COM0
COM8 COM9
COM15
COM112
COM119 COM120
COM127
Fig.10-2 Partial display image 1 (duty cycle ratio=1/120, COM0=0)
Ver.2003-04-08
- 39 -
NJU6680
COM0
COM8 COM9
COM15
COM112
COM119 COM120
COM127
Fig.10-3 Partial display image 2 (duty cycle ratio=1/16, COM0=112)
COM0
COM8 COM9
COM15
COM112
COM119 COM120
COM127
Fig.10-4 Partial display image 3 (duty cycle ratio=1/112, COM0=9)
40 - 40 Ver.2003-04-08
NJU6680
Examples for instruction sequence
Start of Initialization
Power ON (VDD-VSS) with keeping RES=L
Wait for the power ON (VDD-VSS) stabilization
RES=H
ADC select COM scan direction select Partial display duty set Initial COM0 line set
Internal oscillator ON Boost level set LCD bias set Internal resistor ratio set Contrast level set Power control set (VC=VR=VF=1)
FRC & PWM set Gray scale mode and register set N-line inversion set
Wait for LCD power supply stabilization
End of Initialization
Fig.11 Initialization in using the internal power circuits
Ver.2003-04-08
- 41 -
NJU6680
Start of Initialization
Power ON (VDD-VSS) with keeping RES=L
Wait for the power ON (VDD-VSS) stabilization
RES=H
Power save mode ON
ADC select COM scan direction select Partial display duty set Initial COM0 line set
Internal oscillator ON Power control set (VC=VR=VF=0)
FRC & PWM set Gray scale mode and register set N-line inversion set
External save mode ON
Power save mode OFF
Wait for LCD power supply stabilization
End of Initialization Fig.12 Initialization in using the external power supply
42 - 42 Ver.2003-04-08
NJU6680
End of Initialization
Initial display line set Page address set Column address set
Display data write
Display ON
End of display data write
Fig.13 Display data write sequence
Optional status
Power save mode ON
Power OFF (VDD-VSS)
End of power OFF (VDD-VSS)
Fig.14 Power OFF sequence
Ver.2003-04-08
- 43 -
NJU6680
Optional status
Display OFF
Power save mode ON
Partial display duty set Initial display line set Initial COM0 line set
Boost level set LCD bias set Internal resistor ratio set Contrast level set
FRC & PWM set Gray scale mode and register set N-line inversion set
Power save mode OFF
Wait for LCD power supply stabilization
Display data write 1Display ON
End of Initialization
Fig.15 Partial display sequence
44 - 44 Ver.2003-04-08
NJU6680
ABSOLUTE MAXIMUM RATING
(Ta=25C) PARAMETER Supply Voltage(1) Supply Voltage(2) Supply Voltage(3) Input Voltage Operating Temperature Strage Temperature TCP Chip SYMBOL VDD , VCI V0 , VOUT V1,V2,V3,V4 VIN TOPR TSTG RATINGS -0.3 to +4.0 VSS-0.3 to VSS+18.0 -0.3 to V0+0.3 -0.3 to VDD+0.3 -40 to +85 -55 to +100 -55 to +125 UNIT V V V V C C
V0 VCI VSS VSS
Note 1) All voltages are relative to VSS=0V reference. The relationship among the supply voltages should be maintained in the following condition: VSSVer.2003-04-08
- 45 -
NJU6680
ELECTRICAL CHARACTERISTICS
PARAMETER Operating voltage(1) SYMBOL VDD CONDITIONS VDD =2.7V 6-times boost VDD=2.2 to 3.0V 3,4,5-times boost VDD=2.2 to 3.6V VLCD=V0-VSS D0 to D1 Terminal IOH=-0.5mA IOL= 0.5mA V0=8.0V In Power Save Mode Ta=25C Rf=270k RES terminal VDD-VSS VDD=2.2 to 3.0V 6-times boost (VDD=2.2 to 3.6V, VSS=0V, Ta=-40 to +85C) MIN. TYP. MAX. UNIT NOTE 2.2 3.6 V 5 2.7 2.775 2.875 VDD VDD 6.0 0.6V0 VSS 0.8VDD VSS 0.8VDD VSS -1.0 -3.0 150 1.0 10 3.0 10 3.0 V 3.6 15.0 V0 0.4V0 VDD 0.2VDD VDD 0.2VDD 1.0 3.0 4.5 2.0 180 V V V A A k A pF Hz S S 6 7 8 9 10 -
Operating voltage(2)
VCI V0 V1,V2 V3,V4 VIH VIL VOH VOL ILI IL0 RON Isleep CIN fFR tR tRW
Operating voltage(3) Input High Level Voltage Low Level Output High Level Voltage Low Level Input Leakage Current Output Leakage Current Driver On-resistance Stand-by Current Input Terminal Capacitance Frame Frequency Reset Time Reset "L" level pulse Width
Input Voltage Voltage converter efficiency Voltage Follower operating voltage Voltage converter output on resustance Operating Current Reference Voltage External reference voltage VREF temp.Coefficient
VCI
VDD 95 6.0 -
99 2.0
3.0 16.5 4.0
V % V k
11 -
VREG% No-load V0 RSTEP Voltage regulator "OFF" C1 to C5, COUT=1.0F 6-times boost Ta=25C, VDD=2.75V (Checker board display, No access from MPU, All COM/SEG open) Ta=25C VDD=3.0V
IOUT1 VREF VEXT TC
2.04 2.0 -
400 2.10 -0.125
550 2.16 VDD -
A V V %/C
13 -
46 - 46 Ver.2003-04-08
NJU6680
Note 5) This parameter cannot be guaranteed for the spike voltage during an MPU access. Note 6) Apply to the resistance between each driver (COM, SEG) and power supply (V1,V2,V3,V4) terminals when the voltage difference 0.1V is supplied between these terminals. Note 7) Apply to the condition when the internal power circuits are not used and MPU doesn't access to the LSI. Note 8) Apply to the D7 to D0, E, R/W, RS, CS, PS0 and PS1 terminals. Note 9) Specified the time between the rising edge of the RES signal and the completion of the reset operation. Note 10) Specify the minimum pulse width of the RES signal. Note 11) Apply to the VDD when 6x boost level is used. Note 12) The LCD driving voltage can be adjusted within the operating range of the voltage converter. Note 13) Each of the values is specified by each of the following conditions. POWER SUPPLY SYMBOL SET INSTRUCTION VC VR VF IOUT1 1 1 1 OPERATING CONDITION Voltage converter ON (5 times) Voltage regulator ON Voltage follower ON
Ver.2003-04-08
- 47 -
NJU6680
BUS TIMING CHARACTERISTICS
*
Read/Write operation sequence(80 type MPU)
tcyc8
WR,RD
tCCL tf tAW8 tr tAH8 tCCH
RS,CS
tDS8 tDH8
D7 to D0 Write
tACC8 tOH8
D7 to D0 Read (VSS=0V, VDD=2.2V, Ta=-40 to +85C) Measurement MIN. MAX. UNIT Condition 0 0 330 210 210 120 ns 60 40 15 114 CL=100pF 5 50 15 (VSS=0V, VDD=3.0V, Ta=-40 to +85C) Measurement MIN. MAX. UNIT Condition 0 0 166 70 70 70 ns 30 30 10 50 CL=100pF 5 50 15
PARAMETER Address set up time Address hold time System cycle time Control "H" pulse width Control "L" pulse width Read Write Read Write
SIGNAL RS,CS
SYMBOL tAW8 tAH8 tcyc8 tCCHR tCCHW tCCLR tCCLW tDS8 tDH8 tACC8 tOH8 tr,tf
WR,RD
Data set up time Data hold time RD access time Output disable time Input signal rising, falling edge
D7 to D0 -
PARAMETER Address set up time Address hold time System cycle time Control "H" pulse width Control "L" pulse width Read Write Read Write
SIGNAL RS,CS
SYMBOL tAW8 tAH8 tcyc8 tCCHR tCCHW tCCLR tCCLW tDS8 tDH8 tACC8 tOH8 tr,tf
WR,RD
Data set up time Data hold time RD access time Output disable time Input signal rising, falling edge
D7 to D0 -
48 - 48 Ver.2003-04-08
NJU6680
*
System BUS Sequence (Read / Write) (68-type 1 MPU)
tAW6
R/W RS
tr
Tf tAH6
CS
tDS6 tDH6
D7 to D0 Write
tACC6 tOH6
D7 to D0 Read
PARAMETER Address set up time Address hold time System cycle time Data set up time Data hold time RD access time Output disable time Input signal rising, falling edge
SIGNAL RS,CS
SYMBOL tAW6 tAH6 tcyc6 tDS6 tDH6 tACC6 tOH6 tr,tf
D7 to D0 -
(VSS=0V, VDD=2.2V, Ta=-40 to +85C) Measurement MIN. MAX. UNIT Condition 0 0 350 40 ns 10 128 CL=100pF 5 50 15 (VSS=0V, VDD=3.0V, Ta=-40 to +85C) Measurement MIN. MAX. UNIT Condition 0 0 166 30 ns 10 52 CL=100pF 5 50 15
PARAMETER Address set up time Address hold time System cycle time Data set up time Data hold time RD access time Output disable time Input signal rising, falling edge
SIGNAL RS,CS
SYMBOL tAW6 tAH6 tcyc6 tDS6 tDH6 tACC6 tOH6 tr,tf
D7 to D0 -
Note 14) Apply to the condition that E pin is always fixed to "H".
Ver.2003-04-08
- 49 -
NJU6680
*
System BUS Sequence (Read / Write) (68-type 2 MPU)
tcyc6
E
tAW6
tCCH
tCCL
R/W
tr
tf tAH6
tDS6
tDH6
D7 to D0 Write
tACC6 tOH6
D7 to D0 Read
PARAMETER Address set up time Address hold time System cycle time Enable "H" pulse width Enable "L" pulse width Read Write Read Write
SIGNAL
SYMBOL tAW6 tAH6 tcyc6 tCCHR tCCHW tCCLR tCCLW tDS6 tDH6 tACC6 tOH6 tr, tf
RS,CS
E
Data set up time Data hold time RD access time Output disable time Input signal rising, falling edge
D7 to D0 -
(VSS=0V, VDD=2.2V, Ta=-40 to +85C) Measurement MIN. MAX. UNIT Condition 0 25 0 350 140 60 140 ns 60 40 10 15 CL=100pF 5 50 15 (VSS=0V, VDD=3.0V, Ta=-40 to +85C) Measurement MIN. MAX. UNIT Condition 0 0 166 70 70 40 ns 40 30 10 15 CL=100pF 5 50 15
PARAMETER Address set up time Address hold time System cycle time Enable "H" pulse width Enable "L" pulse width Read Write Read Write
SIGNAL
SYMBOL tAW6 tAH6 tcyc6 tCCHR tCCHW tCCLR tCCLW tDS6 tDH6 tACC6 tOH6 tr,tf
RS,CS
E
Data set up time Data hold time RD access time Output disable time Input signal rising, falling edge
D7 to D0 -
50 - 50 Ver.2003-04-08
NJU6680
*
Serial Interfave
tCSS tCSH
CS
tSAS tSAH
RS
tscyc tSLW tSHW
SCL
tf
TSDS tr
tSDH
SI
PARAMETER Serial clock cycle SCL "H" pulse width SCL "L" pulse width Address set up time Address hold time Data set up time Data hold time CS-SCL time Rising, falling edge
SIGNAL SCL RS SI CS -
SYMBOL tscyc tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH tr,tf
(VSS=0V, VDD=2.2V, Ta=-40 to +85C) Measurement MIN. MAX. UNIT Condition 110 40 40 60 60 ns 50 60 60 55 15 (VSS=0V, VDD=3.0V, Ta=-40 to +85C) Measurement MIN. MAX. UNIT Condition 55 20 20 30 30 ns 25 30 30 27 15
PARAMETER Serial clock cycle SCL "H" pulse width SCL "L" pulse width Address set up time Address hold time Data set up time Data hold time CS-SCL time Rising, falling edge
SIGNAL SCL RS SI CS -
SYMBOL tscyc tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH tr,tf
Note 15) SPI clock tolerance is 2ppm.
Ver.2003-04-08
- 51 -
NJU6680
LCD Driving Wave Form (Black & White Mode)
FR VDD VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0
C0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 S4 S3 S2 S1 S0 S1 C0-S0 C0-S1
C1
C2
S0
52 - 52 Ver.2003-04-08
NJU6680
APPLICATION CIRCUIT
Example for the application circuits in using the internal power circuits (VC=VR=VF=1)
PS0 (Note1) PS1 CSB RESB
COM0- 127
68 type MPU
RS R/W E DB7 -0
LCD Panel 128 X 128 pixels
VDD + + VSS
VDD VCI VSS
SEG0 - 127
+ Cout
VOUT
+ C5 + C3 C1
C5+ C3+ C1 + + C2 C2 C4 + C4+ C1+ C2+
Reference values: NJU6680 Rf : 270k for fFR=165Hz(typ.) Cout : 1.0[ F] - 4.7[F] C1-C5 : 1.0[ F] - 4.7[F] : 0.47[ F] - 2.0[F] C6 Ra, Rb : Refer to (3-7) Using external Ra and Rb resistors
(Note2)
REF VEXT
INTRS (Note3)
Setting example:
C6 C6 C6 C6 C6 Rb VR Ra + + + + + V0 V4 V3 V2 V1
Note1) PS0=PS1=1 : 68 type MPU interface Note2) REF=1 : Internal reference voltage Note3) INTRS=0 : External Ra and Rb resistors
OSC1 Rf
Fig.16
Ver.2003-04-08
- 53 -
NJU6680
*
MPU Interface Example * 80 type MPU
VCC VCC A0 A1 - A7 /IORQ MPU D7 - D0 /RD /WR /RESET VSS VSS RESET Decoder RS CS CSB D7 - D0 RD RDB WR WRB RESB RES
VDD VDD
NJU6680 PS0 PS1 VSS VSS PS0="1" PS1="1"
* 68 type MPU
VCC VCC A0 A1 - A7 VMA MPU D7 - D0 E R/W /RESET VSS VSS RESET Decoder RS CS CSB D7 - D0 E R/W RES RESB
VDD VDD
NJU6680 PS0 PS1 VSS VSS PS0="1" PS1="0"
* Serial Interface (4-Wire)
VCC VCC A0 A1 - A7 MPU Port1 Port2 Decoder RS CS CSB SI SCL
VDD VDD
NJU6680 PS0 PS0="0" PS1="1"
/RESET VSS VSS RESET
RES RESB VSS VSS
PS1
* Serial Interface (3-Wire)
VCC VCC VDD VDD
A1 - A7 MPU Port1 Port2
Decoder
CS CSB SI SCL PS0 PS0="0" PS1="0" NJU6680
/RESET VSS VSS RESET
RES RESB VSS VSS
PS1
54 - 54 Ver.2003-04-08
NJU6680
*
Connections between the LSI and LCD panel
(1) ADC=0, COM scan direction=0
(2) ADC=1, COM scan direction=0
COM63
NJU6680 (Top View)
COM127
COM127
NJU6680 (Bottom View)
COM63
COM0 SEG0
COM64 SEG127
COM64 SEG127
COM0 SEG0
(COM scan direction) 128X128 pixels
(COM scan direction) 128X128 pixels
(3) ADC=1, COM scan direction=1
(4) ADC=0, COM scan direction=1
(COM scan direction) 128X128 pixels
(COM scan direction) 128X128 pixels
SEG127 COM64
SEG0 COM0
SEG0 COM0
SEG127 COM64
COM127
NJU6680 (Top View)
COM63
COM63
NJU6680 (Bottom View)
COM127
Fig. 17
Ver.2003-04-08
- 55 -
NJU6680
MEMO
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
56 - 56 Ver.2003-04-08

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